Accelerator for intermittent FPGA systems



In this project, I designed an FPGA-based hardware accelerator for matrix-vector calculations in an energy-constrained system. The use case for this is in systems where it's hard or impossible to service the modules, thus they have to harvest energy from the environment. Due to the low amount of energy available, the calculation may have to be paused until there's enough energy harvested sometime later. For some calculations that requires matrix-vector calculations, such as machine learning, it's advantageous to offload those calculations to a hardware accelerator.

My Role

My role in this project is the lead designer and tester for the actual accelerator that will be implemented on the FPGA part of the system. I'm also responsible to make sure that the FPGA system correctly interfaces with the main microcontroller system.

Skills Learned

From this project, I learned a lot about FPGA design. More specifically, I got to work with complex behavior design, such as the control module and the memory module. I also gained a lot of experience writing test scripts and debugging designs. In previous classes I didn't get a chance to work this extensively in the testing phase.


My main contributions are multiple revisions of the accelerator, both for matrix-matrix calculations and matrix-vector calculations. I also designed a software interface for the microcontroller so that it can interface with the accelerator correctly.